The present invention relates generally to methods and apparatuses for performing convolution operations, and more particularly to a method and apparatus for performing a convolution operation rapidly.
Convolution operations are performed in many communications devices, such as modems and receivers, in general. Consequently, the speed of these operations has a direct impact on the overall speed of these devices.
Calculating a convolution using direct calculations can be a time consuming, memory hungry operation. In general, for an output block of size N, filter length size M, direct convolution will require 2NM+N memory access to calculate all N outputs. For example, assuming a block size of 48 samples, a filter of length 96, requires 9216 memory accesses for the direct convolution. Reducing the memory accesses will significantly speed up the performance of the processor, such as Digital Signal Processors (DSPs) and Reduced Instruction Set Central Processing Unit (RISC) processors.
The present invention is therefore directed to the problem of developing a method and apparatus for performing a convolution operation rapidly in a processor based device.
The present invention solves this problem by converting the convolution operation into a commands that function efficiently due to the architecture of the RISC processor. Thus, the present invention provides a technique for performing bandwidth efficient convolution operations, as well as other filtering operations.